VREV32
Vector Reverse in words
Vector Reverse in words reverses the order of 8-bit or 16-bit
elements in each word of the vector, and places the result in the
corresponding destination vector.
There is no distinction between data types, other than size.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
1
0
0
VREV32{<c>}{<q>}.<dt> <Dd>, <Dm>
1
VREV32{<c>}{<q>}.<dt> <Qd>, <Qm>
if UInt(op)+UInt(size) >= 3 then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let container_size : integer = 64 >> UInt(op);
let containers : integer = 64 DIV container_size;
let elements_per_container : integer = container_size DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
VREV32{<c>}{<q>}.<dt> <Dd>, <Dm>
1
VREV32{<c>}{<q>}.<dt> <Qd>, <Qm>
if UInt(op)+UInt(size) >= 3 then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let container_size : integer = 64 >> UInt(op);
let containers : integer = 64 DIV container_size;
let elements_per_container : integer = container_size DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the operand,
size
<dt>
00
8
01
16
1x
RESERVED
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
var result : bits(64);
var element : integer;
var rev_element : integer;
for r = 0 to regs-1 do
element = 0;
for c = 0 to containers-1 do
rev_element = (element + elements_per_container) - 1;
for e = 0 to elements_per_container-1 do
result[rev_element*:esize] = D(m+r)[element*:esize];
element = element + 1;
rev_element = rev_element - 1;
end;
end;
D(d+r) = result;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1