VRINTN (Advanced SIMD)
Vector Round floating-point to integer to Nearest
Vector Round floating-point to integer to Nearest rounds a vector of
floating-point values to integral floating-point values of the same
size using the Round to Nearest rounding mode. A zero input gives a
zero result with the same sign, an infinite input gives an infinite
result with the same sign, and a NaN is propagated as for normal
arithmetic.
Related encodings: See Advanced SIMD two registers misc for the T32 instruction set, or Advanced SIMD two registers misc for the A32 instruction set.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
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VRINTN{<q>}.<dt> <Dd>, <Dm>
1
VRINTN{<q>}.<dt> <Qd>, <Qm>
if op[2] != op[0] then See("Related encodings"); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
if (size == '01' && !IsFeatureImplemented(FEAT_FP16)) || size IN {'00', '11'} then Undefined(); end;
// Rounding encoded differently from other VCVT and VRINT instructions
let rounding : FPRounding = FPDecodeRM(op[2]::NOT(op[1]));
let exact : boolean = FALSE;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
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VRINTN{<q>}.<dt> <Dd>, <Dm>
1
VRINTN{<q>}.<dt> <Qd>, <Qm>
if op[2] != op[0] then See("Related encodings"); end;
if InITBlock() then UnpredictableProcedure(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
if (size == '01' && !IsFeatureImplemented(FEAT_FP16)) || size IN {'00', '11'} then Undefined(); end;
// Rounding encoded differently from other VCVT and VRINT instructions
let rounding : FPRounding = FPDecodeRM(op[2]::NOT(op[1]));
let exact : boolean = FALSE;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let fpcr : FPCR_Type = StandardFPCR();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let operand1 : bits(esize) = D(m+r)[e*:esize];
let result : bits(esize) = FPRoundInt{}(operand1, fpcr, rounding, exact);
D(d+r)[e*:esize] = result;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1