VRSQRTS
Vector Reciprocal Square Root Step
Vector Reciprocal Square Root Step multiplies the elements
of one vector by the corresponding elements of another vector, subtracts
each of the products from 3.0, divides these results by 2.0, and
places the results into the elements of the destination vector.
The operand and result elements are floating-point numbers.
For details of the operation performed by this instruction
see Floating-point reciprocal estimate and step.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Newton-Raphson iteration
For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate the reciprocal of the square root of a number, see Floating-point reciprocal estimate and step.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
0
0
1
1
1
1
1
1
0
VRSQRTS{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VRSQRTS{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
0
VRSQRTS{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VRSQRTS{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
if sz == '1' && InITBlock() then UnpredictableProcedure(); end;
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
size == '01' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
D(d+r)[e*:esize] = FPRSqrtStep{esize}(D(n+r)[e*:esize], D(m+r)[e*:esize]);
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1