VSHLL
Vector Shift Left Long
Vector Shift Left Long takes each element in a doubleword
vector, left shifts them by an immediate value, and places the results
in a quadword vector.
The operand elements can be:
8-bit, 16-bit, or 32-bit signed integers.
8-bit, 16-bit, or 32-bit unsigned integers.
8-bit, 16-bit, or 32-bit untyped integers, maximum shift only.
The result elements are twice the length of the operand elements.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
and
T2
)
.
1
1
1
1
0
0
1
1
!= 000xxx
1
0
1
0
0
0
1
VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>
if imm6 == '000xxx' then See("Related encodings"); end;
if imm6 IN {'001000', '010000', '100000'} then See("VMOVL"); end;
if Vd[0] == '1' then Undefined(); end;
let esize : integer{} = 8 << HighestSetBitNZ(imm6[5:3]);
let elements : integer = 64 DIV esize;
let shift_amount : integer = UInt(imm6) - esize;
let unsigned : boolean = (U == '1');
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
0
0
0
VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>
if size == '11' || Vd[0] == '1' then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let shift_amount : integer = esize;
let unsigned : boolean = FALSE; // Or TRUE without change of functionality
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
1
1
1
1
1
1
1
1
!= 000xxx
1
0
1
0
0
0
1
VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>
if imm6 == '000xxx' then See("Related encodings"); end;
if imm6 IN {'001000', '010000', '100000'} then See("VMOVL"); end;
if Vd[0] == '1' then Undefined(); end;
let esize : integer{} = 8 << HighestSetBitNZ(imm6[5:3]);
let elements : integer = 64 DIV esize;
let shift_amount : integer = UInt(imm6) - esize;
let unsigned : boolean = (U == '1');
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
0
VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>
if size == '11' || Vd[0] == '1' then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let shift_amount : integer = esize;
let unsigned : boolean = FALSE; // Or TRUE without change of functionality
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
<c>
For the "A1" and "A2" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1" and "T2" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
The data size for the elements of the operand. The following table shows the permitted values and their encodings:
<size>
Encoding T1/A1
Encoding T2/A2
8
Encoded as imm6<5:3> =0b001
Encoded as size =0b00
16
Encoded as imm6<5:4> =0b01
Encoded as size =0b01
32
Encoded as imm6<5> = 1
Encoded as size =0b10
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<imm>
The immediate value. <imm> must lie in the range 1 to <size>, and:
If <size> == <imm>, the encoding is T2/A2.
Otherwise, the encoding is T1/A1, and:
If <size> == 8, <imm> is encoded in imm6<2:0>.
If <size> == 16, <imm> is encoded in imm6<3:0>.
If <size> == 32, <imm> is encoded in imm6<4:0>.
<type>
The data type for the elements of the operand. It must be one of:
S
Signed. In encoding T1/A1, encoded as U = 0.
U
Unsigned. In encoding T1/A1, encoded as U = 1.
I
Untyped integer, Available only in encoding T2/A2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for e = 0 to elements-1 do
let opelt : bits(esize) = Din(m)[e*:esize];
let element : integer = if unsigned then UInt(opelt) else SInt(opelt);
let result : integer = element << shift_amount;
Q(d>>1)[e*:(2*esize)] = result[2*esize-1:0];
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1