VST4 (multiple 4-element structures)
Store multiple 4-element structures from four registers
Store multiple 4-element structures from four registers stores
multiple 4-element structures to memory from four registers, with
interleaving. For more information, see
Element and structure load/store
instructions. Every element of each register is saved. For details
of the addressing mode, see Advanced SIMD
addressing mode.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information, see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST4 (multiple 4-element structures).
Related encodings: See Advanced SIMD element or structure load/store for the T32 instruction set, or Advanced SIMD element or structure load/store for the A32 instruction set.
For more information about the variants of this instruction, see Advanced SIMD addressing mode.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
1
0
0
0
0
0
0
0
0
x
1
1
1
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' then Undefined(); end;
if itype != '000x' then See("Related encodings"); end;
let inc : integer = if itype[0] == '0' then 1 else 2;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
1
1
1
1
1
0
0
1
0
0
0
0
0
0
x
1
1
1
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' then Undefined(); end;
if itype != '000x' then See("Related encodings"); end;
let inc : integer = if itype[0] == '0' then 1 else 2;
let alignment : integer{} = if align == '00' then 1 else 4 << UInt(align);
let ebytes : integer{} = 1 << UInt(size);
let elements : integer = 8 DIV ebytes;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
The memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN. If the instruction specifies writeback, then that register becomes UNKNOWN. This behavior does not affect any other memory locations.
<c>
For the "A1 Offset" and "A1 Post-indexed" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 Offset" and "T1 Post-indexed" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
Is the data size,
size
<size>
00
8
01
16
10
32
<list>
Is a list containing the 64-bit names of the SIMD&FP registers.
The list must be one of:
{ <Dd>, <Dd+1>, <Dd+2>, <Dd+3> }
Single-spaced registers, encoded in the "itype" field as 0b0000.
{ <Dd>, <Dd+2>, <Dd+4>, <Dd+6> }
Double-spaced registers, encoded in the "itype" field as 0b0001.
The register <Dd> is encoded in the "D:Vd" field.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field.
<align>
Is the optional alignment.
Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and is encoded in the "align" field as 0b00.
Whenever <align> is present, the permitted values are:
64
64-bit alignment, encoded in the "align" field as 0b01.
128
128-bit alignment, encoded in the "align" field as 0b10.
256
256-bit alignment, encoded in the "align" field as 0b11.
: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode.
<Rm>
Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
var address : bits(32) = R(n);
let nontemporal : boolean = FALSE;
let privileged : boolean = PSTATE.EL != EL0;
let tagchecked : boolean = FALSE;
let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_STORE, nontemporal,
tagchecked, privileged);
if !IsAlignedSize(address, alignment) then
let fault : FaultRecord = AlignmentFault(accdesc, ZeroExtend{64}(address));
AArch32_Abort(fault);
end;
for e = 0 to elements-1 do
MemU{8*ebytes}(address ) = D(d)[e*:(8*ebytes)];
MemU{8*ebytes}(address+ebytes ) = D(d2)[e*:(8*ebytes)];
MemU{8*ebytes}(address+2*ebytes) = D(d3)[e*:(8*ebytes)];
MemU{8*ebytes}(address+3*ebytes) = D(d4)[e*:(8*ebytes)];
address = address + 4*ebytes;
end;
if wback then
if register_index then
R(n) = R(n) + R(m);
else
R(n) = R(n) + 32;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1