VTBL, VTBX
Vector Table Lookup and Extension
Vector Table Lookup uses byte indexes in a control vector
to look up byte values in a table and generate a new vector. Indexes
out of range return 0.
Vector Table Extension works in the same way, except that
indexes out of range leave the destination element unchanged.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
VTBL{<c>}{<q>}.8 <Dd>, <list>, <Dm>
1
VTBX{<c>}{<q>}.8 <Dd>, <list>, <Dm>
let is_vtbl : boolean = (op == '0');
let length : integer = UInt(len)+1;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
if n+length > 32 then UnpredictableProcedure(); end;
n + length > 32
One or more of the SIMD and floating-point registers are UNKNOWN. This behavior does not affect any general-purpose registers.
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
VTBL{<c>}{<q>}.8 <Dd>, <list>, <Dm>
1
VTBX{<c>}{<q>}.8 <Dd>, <list>, <Dm>
let is_vtbl : boolean = (op == '0');
let length : integer = UInt(len)+1;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
if n+length > 32 then UnpredictableProcedure(); end;
n + length > 32
One or more of the SIMD and floating-point registers are UNKNOWN. This behavior does not affect any general-purpose registers.
<c>
For the "A1 VTBL" and "A1 VTBX" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 VTBL" and "T1 VTBX" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<list>
The vectors containing the table. It must be one of:
{<Dn>}
Encoded as len = 0b00.
{<Dn>, <Dn+1>}
Encoded as len = 0b01.
{<Dn>, <Dn+1>, <Dn+2>}
Encoded as len = 0b10.
{<Dn>, <Dn+1>, <Dn+2>, <Dn+3>}
Encoded as len = 0b11.
<Dm>
Is the 64-bit name of the SIMD&FP source register holding the indices, encoded in the "M:Vm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
// Create 256-bit = 32-byte table variable, with zeros in entries that will not be used.
let table3 : bits(64) = if length == 4 then D(n+3) else Zeros{64};
let table2 : bits(64) = if length >= 3 then D(n+2) else Zeros{64};
let table1 : bits(64) = if length >= 2 then D(n+1) else Zeros{64};
let table : bits(256) = table3 :: table2 :: table1 :: D(n);
for i = 0 to 7 do
let index : integer = UInt(D(m)[i*:8]);
if index < 8*length then
D(d)[i*:8] = table[index*:8];
else
if is_vtbl then
D(d)[i*:8] = Zeros{8};
// else D[d]<i*:8> unchanged
end;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1