VTRN
Vector Transpose
Vector Transpose treats the elements of its operand vectors
as elements of 2 x 2 matrices, and transposes the matrices.
The elements of the vectors can be 8-bit, 16-bit, or 32-bit.
There is no distinction between data types.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
This instruction is a data-independent-time instruction as described in About the DIT bit.
This instruction is used by the aliases
VUZP (alias)
Never
VZIP (alias)
Never
See
below for details of when each alias is preferred.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
VTRN{<c>}{<q>}.<dt> <Dd>, <Dm>
1
VTRN{<c>}{<q>}.<dt> <Qd>, <Qm>
if size == '11' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
VTRN{<c>}{<q>}.<dt> <Dd>, <Dm>
1
VTRN{<c>}{<q>}.<dt> <Qd>, <Qm>
if size == '11' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
size
<dt>
00
8
01
16
10
32
11
RESERVED
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
Alias Conditions
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let h : integer = elements DIV 2;
for r = 0 to regs-1 do
if d == m then
D(d+r) = ARBITRARY : bits(64);
else
for e = 0 to h-1 do
D(d+r)[(2*e+1)*:esize] = Din(m+r)[(2*e)*:esize];
D(m+r)[(2*e)*:esize] = Din(d+r)[(2*e+1)*:esize];
end;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1