VUSMMLA
Widening 8-bit mixed integer matrix multiply-accumulate into 2x2 matrix
The widening integer matrix multiply-accumulate instruction multiplies the
2x8 matrix of unsigned 8-bit integer values held in the first source vector by the
8x2 matrix of signed 8-bit integer values in the second source vector. The
resulting 2x2 32-bit integer matrix product is destructively added to
the 32-bit integer matrix accumulator held in the destination vector. This
is equivalent to performing an 8-way dot product per destination element.
From Armv8.2, this is an OPTIONAL instruction. ID_ISAR6.I8MM
indicates whether this instruction is supported in the T32 and A32 instruction sets.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
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VUSMMLA{<q>}.S8 <Qd>, <Qn>, <Qm>
if !IsFeatureImplemented(FEAT_AA32I8MM) then Undefined(); end;
var op1_unsigned : boolean;
var op2_unsigned : boolean;
case B::U of
when '00' => op1_unsigned = FALSE; op2_unsigned = FALSE;
when '01' => op1_unsigned = TRUE; op2_unsigned = TRUE;
when '10' => op1_unsigned = TRUE; op2_unsigned = FALSE;
when '11' => Undefined();
end;
if Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
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VUSMMLA{<q>}.S8 <Qd>, <Qn>, <Qm>
if InITBlock() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_AA32I8MM) then Undefined(); end;
var op1_unsigned : boolean;
var op2_unsigned : boolean;
case B::U of
when '00' => op1_unsigned = FALSE; op2_unsigned = FALSE;
when '01' => op1_unsigned = TRUE; op2_unsigned = TRUE;
when '10' => op1_unsigned = TRUE; op2_unsigned = FALSE;
when '11' => Undefined();
end;
if Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
<q>
See Standard assembler syntax fields.
<Qd>
Is the 128-bit name of the SIMD&FP third source and destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
CheckAdvSIMDEnabled();
let operand1 : bits(128) = Q(n>>1);
let operand2 : bits(128) = Q(m>>1);
let addend : bits(128) = Q(d>>1);
Q(d>>1) = MatMulAdd(addend, operand1, operand2, op1_unsigned, op2_unsigned);
2026-03-12 12:23:09
2025-09_rel_asl1