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B

Branch causes a branch to a target address.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 , T3 and T4 ) .

A1

Decode for this encoding

let imm32 : bits(32) = SignExtend{}(imm24::'00');

T1

Decode for this encoding

if cond == '1110' then See("UDF"); end; if cond == '1111' then See("SVC"); end; let imm32 : bits(32) = SignExtend{}(imm8::'0'); if InITBlock() then UnpredictableProcedure(); end;

T2

Decode for this encoding

let imm32 : bits(32) = SignExtend{}(imm11::'0'); if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;

T3

Decode for this encoding

if cond[3:1] == '111' then See("Related encodings"); end; let imm32 : bits(32) = SignExtend{}(S::J2::J1::imm6::imm11::'0'); if InITBlock() then UnpredictableProcedure(); end;

T4

Decode for this encoding

let I1 : bit = NOT(J1 XOR S); let I2 : bit = NOT(J2 XOR S); let imm32 : bits(32) = SignExtend{}(S::I1::I2::imm10::imm11::'0'); if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;

Assembler Symbols