Operation

if !Halted() then Undefined(); end; if EL2Enabled() && PSTATE.EL == EL0 then let tge : bit = if ELUsingAArch32(EL2) then HCR().TGE else HCR_EL2().TGE; if tge == '1' then Undefined(); end; end; if PSTATE.EL != EL0 || ELUsingAArch32(EL1) then if PSTATE.M == M32_Monitor then SCR().NS = '0'; end; if PSTATE.EL != EL2 then AArch32_WriteMode(M32_Svc); PSTATE.E = SCTLR().EE; if IsFeatureImplemented(FEAT_PAN) && SCTLR().SPAN == '0' then PSTATE.PAN = '1'; end; Rmode(14, M32_Svc) = ARBITRARY : bits(32); // LR_svc SPSR_svc() = ARBITRARY : bits(32); else PSTATE.E = HSCTLR().EE; ELR_hyp() = ARBITRARY : bits(32); HSR() = ARBITRARY : bits(32); SPSR_hyp() = ARBITRARY : bits(32); end; DLR() = ARBITRARY : bits(32); DSPSR() = ARBITRARY : bits(32); else // Targeting EL1 using AArch64 AArch64_MaybeZeroRegisterUppers(); MaybeZeroSVEUppers(EL1); PSTATE.nRW = '0'; PSTATE.SP = '1'; PSTATE.EL = EL1; if IsFeatureImplemented(FEAT_PAN) && SCTLR_EL1().SPAN == '0' then PSTATE.PAN = '1'; end; if IsFeatureImplemented(FEAT_UAO) then PSTATE.UAO = '0'; end; ELR_EL1() = ARBITRARY : bits(64); ESR_EL1() = ARBITRARY : bits(64); SPSR_EL1() = ARBITRARY : bits(64); DLR_EL0() = ARBITRARY : bits(64); DSPSR_EL0() = ARBITRARY : bits(64); // SCTLR_EL1.IESB might be ignored in Debug state. if (IsFeatureImplemented(FEAT_IESB) && SCTLR_EL1().IESB == '1' && !ConstrainUnpredictableBool(Unpredictable_IESBinDebug)) then SynchronizeErrors(); end; end; UpdateEDSCRFields(); // Update EDSCR PE state flags