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ESB

Error Synchronization Barrier is an error synchronization event that might also update DISR and VDISR. This instruction can be used at all Exception levels and in Debug state.

In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. For more information, see RAS PE architecture and Arm^® Reliability, Availability, and Serviceability (RAS) System Architecture, for A-profile architecture (ARM IHI 0100).

If FEAT_RAS is not implemented, this instruction executes as a NOP.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_RAS)

Decode for this encoding

if !IsFeatureImplemented(FEAT_RAS) then ExecuteAsNOP(); end; if cond != '1110' then UnpredictableProcedure(); end; // ESB must be encoded with AL condition

CONSTRAINED UNPREDICTABLE behavior

If cond != '1110', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes unconditionally.
• The instruction executes conditionally.

T1
(FEAT_RAS)

Decode for this encoding

if !IsFeatureImplemented(FEAT_RAS) then ExecuteAsNOP(); end; if InITBlock() then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes unconditionally.
• The instruction executes conditionally.