HVC -- AArch32

This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

HVC -- AArch32

HVC

Hypervisor Call causes a Hypervisor Call exception. For more information, see Hypervisor Call (HVC) exception. Software executing at EL1 can use this instruction to call the hypervisor to request a service.

The HVC instruction is UNDEFINED:

When EL3 is implemented and using AArch64, and SCR_EL3.HCE is set to 0.
In Non-secure EL1 modes when EL3 is implemented and using AArch32, and SCR.HCE is set to 0.
When EL3 is not implemented and either HCR_EL2.HCD is set to 1 or HCR.HCD is set to 1.
When EL2 is not implemented.
In Secure state, if EL2 is not enabled in the current Security state.
In User mode.

The HVC instruction is CONSTRAINED UNPREDICTABLE in Hyp mode when EL3 is implemented and using AArch32, and SCR.HCE is set to 0.

On executing an HVC instruction, the HSR, Hyp Syndrome Register reports the exception as a Hypervisor Call exception, using the EC value 0x12, and captures the value of the immediate argument, see Use of the HSR.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	1	0	1	0	0	imm12												0	1	1	1	imm4
cond									opc

Encoding

HVC{<q>} {#}<imm16>

Decode for this encoding

if cond != '1110' then UnpredictableProcedure(); end; let imm16 : bits(16) = imm12::imm4;

CONSTRAINED UNPREDICTABLE behavior

If cond != '1110', then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction executes unconditionally.
The instruction executes conditionally.

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	1	1	1	1	1	1	0	imm4				1	0	0	0	imm12
											o1							o2

Encoding

HVC{<q>} {#}<imm16>

Decode for this encoding

let imm16 : bits(16) = imm4::imm12; if InITBlock() then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<q>	See Standard assembler syntax fields. An HVC instruction must be unconditional.

<imm16>	For the "A1" variant: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm12:imm4" field. This value is for assembly and disassembly only. It is reported in the HSR but otherwise is ignored by hardware. An HVC handler might interpret imm16, for example to determine the required service.
	For the "T1" variant: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm4:imm12" field. This value is for assembly and disassembly only. It is reported in the HSR but otherwise is ignored by hardware. An HVC handler might interpret imm16, for example to determine the required service.

Operation

EncodingSpecificOperations(); if PSTATE.EL IN {EL0, EL3} || !EL2Enabled() then Undefined(); end; var hvc_enable : bit; if HaveEL(EL3) then if ELUsingAArch32(EL3) then if SCR().HCE == '0' && PSTATE.EL == EL2 then UnpredictableProcedure(); end; hvc_enable = SCR().HCE; else hvc_enable = SCR_EL3().HCE; end; else hvc_enable = if ELUsingAArch32(EL2) then NOT(HCR().HCD) else NOT(HCR_EL2().HCD); end; if hvc_enable == '0' then Undefined(); else AArch32_CallHypervisor(imm16); end;

CONSTRAINED UNPREDICTABLE behavior

If ELUsingAArch32(EL3) && SCR.HCE == '0' && PSTATE.EL == EL2, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.

2025-09_rel_asl1 2026-03-12 12:57:38