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LDRSHT

Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses.

The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.

LDRSHT is UNPREDICTABLE in Hyp mode.

The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.

The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 ) .

A1

Decode for this encoding

let t : integer = UInt(Rt); let n : integer = UInt(Rn); let postindex : boolean = TRUE; let add : boolean = (U == '1'); let register_form : boolean = FALSE; let imm32 : bits(32) = ZeroExtend{}(imm4H::imm4L); let m : integer = ARBITRARY : integer; if t == 15 || n == 15 || n == t then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If n == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction uses post-indexed addressing with the base register as PC. This is handled as described in Using R15.
• The instruction is treated as if bit[24] == '1' and bit[21] == '0'. The instruction uses immediate offset addressing with the base register as PC, without writeback.

If n == t && n != 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.

A2

Decode for this encoding

let t : integer = UInt(Rt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let postindex : boolean = TRUE; let add : boolean = (U == '1'); let register_form : boolean = TRUE; let imm32 : bits(32) = ARBITRARY : bits(32); if t == 15 || n == 15 || n == t || m == 15 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If n == t && n != 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.

T1

Decode for this encoding

if Rn == '1111' then See("LDRSH (literal)"); end; let t : integer = UInt(Rt); let n : integer = UInt(Rn); let postindex : boolean = FALSE; let add : boolean = TRUE; let register_form : boolean = FALSE; let imm32 : bits(32) = ZeroExtend{}(imm8); let m : integer = ARBITRARY : integer; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UnpredictableProcedure(); end;

Assembler Symbols