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PKHBT, PKHTB -- AArch32
Base Instructions
SIMD&FP Instructions
A32 Instructions by Encoding
T32 Instructions by Encoding
Shared Pseudocode
Proprietary Notice

PKHBT, PKHTB

Pack Halfword combines one halfword of its first operand with the other halfword of its shifted second operand.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111101101000RnRdimm5tb01Rm
cond

Encoding for the PKHBT variant

Applies when (tb == 0)

PKHBT{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, LSL #<imm>}

Encoding for the PKHTB variant

Applies when (tb == 1)

PKHTB{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, ASR #<imm>}

Decode for all variants of this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let tbform : boolean = (tb == '1'); let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(tb::'0', imm5); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

T1

15141312111098765432101514131211109876543210
111010101100Rn(0)imm3Rdimm2tb0Rm
op1ST

Encoding for the PKHBT variant

Applies when (tb == 0)

PKHBT{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, LSL #<imm>} // (tbform == FALSE)

Encoding for the PKHTB variant

Applies when (tb == 1)

PKHTB{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, ASR #<imm>} // (tbform == TRUE)

Decode for all variants of this encoding

if S == '1' || T == '1' then Undefined(); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let tbform : boolean = (tb == '1'); let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(tb::'0', imm3::imm2); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>

Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>

Is the second general-purpose source register, encoded in the "Rm" field.

<imm>

For the "A1 PKHBT" and "A1 PKHTB" variants: the shift to apply to the value read from <Rm>, encoded in the "imm5" field.

For PKHBT, it is one of:

omitted
No shift, encoded as 0b00000.
1-31
Left shift by specified number of bits, encoded as a binary number.

For PKHTB, it is one of:

omitted
Instruction is a pseudo-instruction and is assembled as though PKHBT{<c>}{<q>} <Rd>, <Rm>, <Rn> had been written.
1-32
Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as 0b00000. Other shift amounts are encoded as binary numbers.

Note

An assembler can permit <imm> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly.

For the "T1 PKHBT" and "T1 PKHTB" variants: the shift to apply to the value read from <Rm>, encoded in the "imm3:imm2" field.

For PKHBT, it is one of:

omitted
No shift, encoded as 0b00000.
1-31
Left shift by specified number of bits, encoded as a binary number.

For PKHTB, it is one of:

omitted
Instruction is a pseudo-instruction and is assembled as though PKHBT{<c>}{<q>} <Rd>, <Rm>, <Rn> had been written.
1-32
Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as 0b00000. Other shift amounts are encoded as binary numbers.

Note

An assembler can permit <imm> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let operand2 : bits(32) = Shift{}(R(m), shift_t, shift_n, PSTATE.C); // PSTATE.C ignored R(d)[15:0] = if tbform then operand2[15:0] else R(n)[15:0]; R(d)[31:16] = if tbform then R(n)[31:16] else operand2[31:16]; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.

Base Instructions
SIMD&FP Instructions
A32 Instructions by Encoding
T32 Instructions by Encoding
Shared Pseudocode
Proprietary Notice

2025-09_rel_asl1 2026-03-12 12:57:38

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