This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

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REVSH

Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

Decode for this encoding

let d : integer = UInt(Rd); let m : integer = UInt(Rm); if d == 15 || m == 15 then UnpredictableProcedure(); end;

T1

Decode for this encoding

let d : integer = UInt(Rd); let m : integer = UInt(Rm);

T2

Decode for this encoding

let d : integer = UInt(Rd); let m : integer = UInt(Rm); let n : integer = UInt(Rn); // Armv8-A removes UNPREDICTABLE for R13 if m != n || d == 15 || m == 15 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If m != n, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes with the additional decode: m = UInt(Rn);.
• The instruction executes with the additional decode: m = UInt(Rm);.
• The value in the destination register is unknown.

Assembler Symbols