RFE, RFEDA, RFEDB, RFEIA, RFEIB -- AArch32

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RFE, RFEDA, RFEDB, RFEIA, RFEIB

Return From Exception loads two consecutive memory locations using an address in a base register:

The word loaded from the lower address is treated as an instruction address. The PE branches to it.
The word loaded from the higher address is used to restore PSTATE. This word must be in the format of an SPSR.

An address adjusted by the size of the data loaded can optionally be written back to the base register.

The PE checks the value of the word loaded from the higher address for an illegal return event. See Illegal return events from AArch32 state.

RFE is UNDEFINED in Hyp mode and CONSTRAINED UNPREDICTABLE in User mode.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	0	P	U	0	W	1	Rn				(0)	(0)	(0)	(0)	(1)	(0)	(1)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
									S		L					op											mode

Encoding for the Decrement After variant

Applies when (P == 0 && U == 0)

RFEDA{<c>}{<q>} <Rn>{!} // (Preferred syntax)

RFEFA{<c>}{<q>} <Rn>{!} // (Alternate syntax, Full Ascending stack)

Encoding for the Decrement Before variant

Applies when (P == 1 && U == 0)

RFEDB{<c>}{<q>} <Rn>{!} // (Preferred syntax)

RFEEA{<c>}{<q>} <Rn>{!} // (Alternate syntax, Empty Ascending stack)

Encoding for the Increment After variant

Applies when (P == 0 && U == 1)

RFE{IA}{<c>}{<q>} <Rn>{!} // (Preferred syntax)

RFEFD{<c>}{<q>} <Rn>{!} // (Alternate syntax, Full Descending stack)

Encoding for the Increment Before variant

Applies when (P == 1 && U == 1)

RFEIB{<c>}{<q>} <Rn>{!} // (Preferred syntax)

RFEED{<c>}{<q>} <Rn>{!} // (Alternate syntax, Empty Descending stack)

Decode for all variants of this encoding

let n : integer = UInt(Rn); let wback : boolean = (W == '1'); let increment : boolean = (U == '1'); let wordhigher : boolean = (P == U); if n == 15 then UnpredictableProcedure(); end;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	0	0	0	0	0	W	1	Rn				(1)	(1)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
							opc				L					P	M	register_list

Encoding

RFEDB{<c>}{<q>} <Rn>{!} // (Outside or last in IT block, preferred syntax)

RFEFA{<c>}{<q>} <Rn>{!} // (Outside or last in IT block, alternate syntax, Full Ascending stack)

Decode for this encoding

let n : integer = UInt(Rn); let wback : boolean = (W == '1'); let increment : boolean = FALSE; let wordhigher : boolean = FALSE; if n == 15 then UnpredictableProcedure(); end; if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;

T2

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	0	0	1	1	0	W	1	Rn				(1)	(1)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
							opc				L					P	M	register_list

Encoding

RFE{IA}{<c>}{<q>} <Rn>{!} // (Outside or last in IT block, preferred syntax)

RFEFD{<c>}{<q>} <Rn>{!} // (Outside or last in IT block, alternate syntax, Full Descending stack)

Decode for this encoding

let n : integer = UInt(Rn); let wback : boolean = (W == '1'); let increment : boolean = TRUE; let wordhigher : boolean = FALSE; if n == 15 then UnpredictableProcedure(); end; if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	For the "A1 Decrement After", "A1 Decrement Before", "A1 Increment After", and "A1 Increment Before" variants: see Standard assembler syntax fields. <c> must be AL or omitted.
	For the "T1" and "T2" variants: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rn>	Is the general-purpose base register, encoded in the "Rn" field.

!	The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.

IA	For the "Increment After" variant: is an optional suffix to indicate the Increment After variant.
	For the "T2" variant: is an optional suffix for the Increment After form.

RFEFA, RFEEA, RFEFD, and RFEED are pseudo-instructions for RFEDA, RFEDB, RFEIA, and RFEIB respectively, referring to their use for popping data from Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.

Operation

if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL0 then UnpredictableProcedure(); // UNDEFINED or NOP else var address : bits(32) = if increment then R(n) else R(n)-8; if wordhigher then address = address+4; end; let new_pc_value : bits(32) = MemA{32}(address); let spsr : bits(32) = MemA{32}(address+4); if wback then R(n) = if increment then R(n)+8 else R(n)-8; end; AArch32_ExceptionReturn(new_pc_value, spsr); end; end;

CONSTRAINED UNPREDICTABLE behavior

If PSTATE.EL == EL0, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.

2025-09_rel_asl1 2026-03-12 12:57:38