SDIV -- AArch32

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SDIV -- AArch32

SDIV

Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	1	1	1	0	0	0	1	Rd				(1)	(1)	(1)	(1)	Rm				0	0	0	1	Rn
cond									op1							Ra								op2

Encoding

SDIV{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let a : integer = UInt(Ra); if d == 15 || n == 15 || m == 15 || a != 15 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If Ra != '1111', then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction executes as described, with no change to its behavior and no additional side effects.
The instruction executes as described, and the register specified by Ra becomes UNKNOWN.

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	1	0	0	1	Rn				(1)	(1)	(1)	(1)	Rd				1	1	1	1	Rm
									op1							Ra								op2

Encoding

SDIV{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let a : integer = UInt(Ra); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 || a != 15 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If Ra != '1111', then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction executes as described, with no change to its behavior and no additional side effects.
The instruction executes as described, and the register specified by Ra becomes UNKNOWN.

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>	Is the first general-purpose source register holding the dividend, encoded in the "Rn" field.

<Rm>	Is the second general-purpose source register holding the divisor, encoded in the "Rm" field.

Overflow

If the signed integer division 0x80000000 / 0xFFFFFFFF is performed, the pseudocode produces the intermediate integer result +2³¹, that overflows the 32-bit signed integer range. No indication of this overflow case is produced, and the 32-bit result written to <Rd> must be the bottom 32 bits of the binary representation of +2³¹. So the result of the division is 0x80000000.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let dividend : integer = SInt(R(n)); let divisor : integer = SInt(R(m)); var result : integer; if divisor == 0 then result = 0; elsif (dividend < 0) == (divisor < 0) then result = Abs(dividend) DIVRM Abs(divisor); // same signs - positive result else result = -(Abs(dividend) DIVRM Abs(divisor)); // different signs - negative result end; R(d) = result[31:0]; end;

2025-09_rel_asl1 2026-03-12 12:57:38

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	1	0	0	1	Rn				(1)	(1)	(1)	(1)	Rd				1	1	1	1	Rm
									op1							Ra								op2

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	1	0	0	1	Rn				(1)	(1)	(1)	(1)	Rd				1	1	1	1	Rm
									op1							Ra								op2

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	1	0	0	1	Rn				(1)	(1)	(1)	(1)	Rd				1	1	1	1	Rm
									op1							Ra								op2