This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

SEV -- AArch32

SEV

Send Event is a hint instruction. It causes an event to be signaled to all PEs in the multiprocessor system. For more information, see Wait For Event and Send Event.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 1111001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000100
condRimm4imm12

Encoding

SEV{<c>}{<q>}

Decode for this encoding

// No additional decoding required

T1

1514131211109876543210
1011111101000000
hint

Encoding

SEV{<c>}{<q>}

Decode for this encoding

// No additional decoding required

T2

15141312111098765432101514131211109876543210
111100111010(1)(1)(1)(1)10(0)0(0)00000000100
hintoption

Encoding

SEV{<c>}.W

Decode for this encoding

// No additional decoding required

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

Operation

if ConditionPassed() then EncodingSpecificOperations(); SendEvent(); end;


2025-09_rel_asl1 2026-03-12 12:57:38

Copyright © 2010-2025 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.