This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

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SHA1SU1

SHA1 schedule update 1.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_SHA1)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SHA1) then Undefined(); end; if size != '10' then Undefined(); end; if Vd[0] == '1' || Vm[0] == '1' then Undefined(); end; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

T1
(FEAT_SHA1)

Decode for this encoding

if InITBlock() then UnpredictableProcedure(); end; if !IsFeatureImplemented(FEAT_SHA1) then Undefined(); end; if size != '10' then Undefined(); end; if Vd[0] == '1' || Vm[0] == '1' then Undefined(); end; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

Assembler Symbols