This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

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SHASX

Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

T1

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

Assembler Symbols