SMLSD, SMLSDX -- AArch32

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SMLSD, SMLSDX

Signed Multiply Subtract Dual performs two signed 16 x 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand.

Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.

This instruction sets PSTATE.Q to 1 if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	1	1	1	0	0	0	0	Rd				!= 1111				Rm				0	1	M	1	Rn
cond									op1							Ra

Encoding for the SMLSD variant

Applies when (M == 0)

SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>

Encoding for the SMLSDX variant

Applies when (M == 1)

SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>

Decode for all variants of this encoding

if Ra == '1111' then See("SMUSD"); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let a : integer = UInt(Ra); let m_swap : boolean = (M == '1'); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	0	1	0	0	Rn				!= 1111				Rd				0	0	0	M	Rm
									op1							Ra

Encoding for the SMLSD variant

Applies when (M == 0)

SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>

Encoding for the SMLSDX variant

Applies when (M == 1)

SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>

Decode for all variants of this encoding

if Ra == '1111' then See("SMUSD"); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let a : integer = UInt(Ra); let m_swap : boolean = (M == '1'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>	Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>	Is the second general-purpose source register, encoded in the "Rm" field.

<Ra>	Is the third general-purpose source register holding the addend, encoded in the "Ra" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let operand2 : bits(32) = if m_swap then ROR(R(m),16) else R(m); let product1 : integer = SInt(R(n)[15:0]) * SInt(operand2[15:0]); let product2 : integer = SInt(R(n)[31:16]) * SInt(operand2[31:16]); let result : integer = (product1 - product2) + SInt(R(a)); R(d) = result[31:0]; if result != SInt(result[31:0]) then // Signed overflow PSTATE.Q = '1'; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.

2025-09_rel_asl1 2026-03-12 12:57:38