SSAT16 -- AArch32

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SSAT16 -- AArch32

SSAT16

Signed Saturate 16 saturates two signed 16-bit values to a selected signed range.

This instruction sets PSTATE.Q to 1 if the operation saturates.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	1	1	0	1	0	1	0	sat_imm				Rd				(1)	(1)	(1)	(1)	0	0	1	1	Rn
cond									U

Encoding

SSAT16{<c>}{<q>} <Rd>, #<imm>, <Rn>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let saturate_to : integer{} = UInt(sat_imm)+1; if d == 15 || n == 15 then UnpredictableProcedure(); end;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	(0)	1	1	0	0	1	0	Rn				0	0	0	0	Rd				0	0	(0)	(0)	sat_imm
								op1									imm3							imm2

Encoding

SSAT16{<c>}{<q>} <Rd>, #<imm>, <Rn>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let saturate_to : integer{} = UInt(sat_imm)+1; // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<imm>

Is the bit position for saturation, in the range 1 to 16, encoded in the "sat_imm" field as <imm>-1.

<Rn>	Is the general-purpose source register, encoded in the "Rn" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let (result1, sat1) : (bits(saturate_to), boolean) = SignedSatQ{saturate_to}(SInt(R(n)[15:0])); let (result2, sat2) : (bits(saturate_to), boolean) = SignedSatQ{saturate_to}(SInt(R(n)[31:16])); R(d)[15:0] = SignExtend{16}(result1); R(d)[31:16] = SignExtend{16}(result2); if sat1 || sat2 then PSTATE.Q = '1'; end; end;

2025-09_rel_asl1 2026-03-12 12:57:38