This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

STC

Store data to System register calculates an address from a base register value and an immediate offset, and stores a word from the DBGDTRRXint System register to memory. It can use offset, post-indexed, pre-indexed, or unindexed addressing. For information about memory accesses, see Memory accesses.

In an implementation that includes EL2, the permitted STC access to DBGDTRRXint can be trapped to Hyp mode, meaning that an attempt to execute an STC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see HDCR.TDA.

For simplicity, the STC pseudocode does not show this possible trap to Hyp mode.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for all variants of this encoding

if P == '0' && U == '0' && W == '0' then Undefined(); end; let n : integer = UInt(Rn); let cp : integer = 14; let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); let index : boolean = (P == '1'); let add : boolean = (U == '1'); let wback : boolean = (W == '1'); if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If n == 15 && wback, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes without writeback of the base address.
• The instruction executes with writeback to the PC. The instruction is handled as described in Using R15.

T1

Decode for all variants of this encoding

if P == '0' && U == '0' && W == '0' then Undefined(); end; let n : integer = UInt(Rn); let cp : integer = 14; let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); let index : boolean = (P == '1'); let add : boolean = (U == '1'); let wback : boolean = (W == '1'); if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If n == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes without writeback of the base address.
• The instruction executes with writeback to the PC. The instruction is handled as described in Using R15.

Assembler Symbols