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STLEXH -- AArch32

STLEXH

Store-Release Exclusive Halfword stores a halfword from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.

The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release.

For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100011110RnRd(1)(1)101001Rt
condsizeLexord

Encoding

STLEXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]

Decode for this encoding

let d : integer = UInt(Rd); let t : integer = UInt(Rt); let n : integer = UInt(Rn); if d == 15 || t == 15 || n == 15 then UnpredictableProcedure(); end; if d == n || d == t then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If d == t, then one of the following behaviors must occur:

If d == n, then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111010001100RnRt(1)(1)(1)(1)1101Rd
op0LRt2opsz

Encoding

STLEXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]

Decode for this encoding

let d : integer = UInt(Rd); let t : integer = UInt(Rt); let n : integer = UInt(Rn); if d == 15 || t == 15 || n == 15 then UnpredictableProcedure(); end; if d == n || d == t then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If d == t, then one of the following behaviors must occur:

If d == n, then one of the following behaviors must occur:

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:

0
If the operation updates memory.
1
If the operation fails to update memory.
<Rt>

Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>

Is the general-purpose base register, encoded in the "Rn" field.

Aborts and alignment

If a synchronous Data Abort exception is generated by the execution of this instruction:

A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:

If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let address : bits(32) = R(n); if AArch32_ExclusiveMonitorsPass(address,2) then MemO{16}(address) = R(t)[15:0]; R(d) = ZeroExtend{32}('0'); else R(d) = ZeroExtend{32}('1'); end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2025-09_rel_asl1 2026-03-12 12:57:38

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