This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

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SVC

Supervisor Call causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception.

Software can use this instruction as a call to an operating system to provide a service.

In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode:

• If the SVC is executed in Hyp mode.
• If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1

In these cases, the HSR, Hyp Syndrome Register identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR. The immediate field in the HSR:

• If the SVC is unconditional:
  • For the T32 instruction, is the zero-extended value of the imm8 field.
  • For the A32 instruction, is the least-significant 16 bits the imm24 field.
• If the SVC is conditional, is UNKNOWN.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for this encoding

let imm32 : bits(32) = ZeroExtend{}(imm24);

T1

Decode for this encoding

let imm32 : bits(32) = ZeroExtend{}(imm8);