This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

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UXTAH

Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for this encoding

if Rn == '1111' then See("UXTH"); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let rotation : integer = UInt(rotate::'000'); if d == 15 || m == 15 then UnpredictableProcedure(); end;

T1

Decode for this encoding

if Rn == '1111' then See("UXTH"); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let rotation : integer = UInt(rotate::'000'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || m == 15 then UnpredictableProcedure(); end;

Assembler Symbols