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VADDL -- AArch32

VADDL

Vector Add Long adds corresponding elements in two doubleword vectors, and places the results in a quadword vector. Before adding, it sign-extends or zero-extends the elements of both operands.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
1111001U1D!= 11VnVd0000N0M0Vm
sizeop

Encoding

VADDL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>

Decode for this encoding

if size == '11' then See("Related encodings"); end; if Vd[0] == '1' || (op == '1' && Vn[0] == '1') then Undefined(); end; let unsigned : boolean = (U == '1'); let is_vaddw : boolean = (op == '1'); let esize : integer{} = 8 << UInt(size); let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let elements : integer = 64 DIV esize;

T1

15141312111098765432101514131211109876543210
111U11111D!= 11VnVd0000N0M0Vm
sizeop

Encoding

VADDL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>

Decode for this encoding

if size == '11' then See("Related encodings"); end; if Vd[0] == '1' || (op == '1' && Vn[0] == '1') then Undefined(); end; let unsigned : boolean = (U == '1'); let is_vaddw : boolean = (op == '1'); let esize : integer{} = 8 << UInt(size); let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let elements : integer = 64 DIV esize;

Related encodings: See Advanced SIMD data-processing for the T32 instruction set, or Advanced SIMD data-processing for the A32 instruction set.

Assembler Symbols

<c>

For the "A1" variant: see Standard assembler syntax fields. This encoding must be unconditional.

For the "T1" variant: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<dt>

Is the data type for the elements of the second operand vector, encoded in (U :: size):

U size <dt>
0 00 S8
0 01 S16
0 10 S32
1 00 U8
1 01 U16
1 10 U32
<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dn>

Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>

Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for e = 0 to elements-1 do var element1 : integer; if is_vaddw then let op1elt : bits(2*esize) = Qin(n>>1)[e*:(2*esize)]; element1 = if unsigned then UInt(op1elt) else SInt(op1elt); else let op1elt : bits(esize) = Din(n)[e*:esize]; element1 = if unsigned then UInt(op1elt) else SInt(op1elt); end; let op2elt : bits(esize) = Din(m)[e*:esize]; let element2 : integer = if unsigned then UInt(op2elt) else SInt(op2elt); let result : integer = element1 + element2; Q(d>>1)[e*:(2*esize)] = result[2*esize-1:0]; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2025-09_rel_asl1 2026-03-12 12:57:38

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