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VBSL

Vector Bitwise Select sets each bit in the destination to the corresponding bit from the first source operand when the original destination bit was 1, otherwise from the second source operand.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for all variants of this encoding

if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end; if op == '00' then See("VEOR"); end; var operation : VBitOps; if op == '01' then operation = VBitOps_VBSL; end; if op == '10' then operation = VBitOps_VBIT; end; if op == '11' then operation = VBitOps_VBIF; end; let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

T1

Decode for all variants of this encoding

if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end; if op == '00' then See("VEOR"); end; var operation : VBitOps; if op == '01' then operation = VBitOps_VBSL; end; if op == '10' then operation = VBitOps_VBIT; end; if op == '11' then operation = VBitOps_VBIF; end; let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;