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VCADD -- AArch32

VCADD

Vector Complex Add.

This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers:

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_FCMA)

313029282726252423222120191817161514131211109876543210
1111110rot1D0SVnVd1000NQM0Vm
op3op4U

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VCADD{<q>}.<dt> <Dd>, <Dn>, <Dm>, #<rotate>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VCADD{<q>}.<dt> <Qd>, <Qn>, <Qm>, #<rotate>

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FCMA) then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end; if S == '0' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end; let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let esize : integer{} = 16 << UInt(S); let elements : integer = 64 DIV esize; let regs : integer = if Q == '0' then 1 else 2;

T1
(FEAT_FCMA)

15141312111098765432101514131211109876543210
1111110rot1D0SVnVd1000NQM0Vm
op3op4U

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VCADD{<q>}.<dt> <Dd>, <Dn>, <Dm>, #<rotate>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VCADD{<q>}.<dt> <Qd>, <Qn>, <Qm>, #<rotate>

Decode for all variants of this encoding

if InITBlock() then UnpredictableProcedure(); end; if !IsFeatureImplemented(FEAT_FCMA) then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end; if S == '0' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end; let esize : integer{} = 16 << UInt(S); let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let elements : integer = 64 DIV esize; let regs : integer = if Q == '0' then 1 else 2;

Assembler Symbols

<q>

See Standard assembler syntax fields.

<dt>

Is the data type for the elements of the vectors, encoded in S:

S <dt>
0 F16
1 F32
<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>

Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>

Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

<rotate>

Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in rot:

rot <rotate>
0 90
1 270
<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qn>

Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>

Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.


2025-09_rel_asl1 2026-03-12 12:57:38

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