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VCMP -- AArch32

VCMP

Vector Compare compares two floating-point registers, or one floating-point register and zero. It writes the result to the FPSCR flags. These are normally transferred to the PSTATE.{N, Z, C, V} Condition flags by a subsequent VMRS instruction.

This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111111101D110100Vd10size01M0Vm
condo1opc2E

Encoding for the Half-precision scalar variant
(FEAT_FP16)

Applies when (size == 01)

VCMP{<c>}{<q>}.F16 <Sd>, <Sm>

Encoding for the Single-precision scalar variant

Applies when (size == 10)

VCMP{<c>}{<q>}.F32 <Sd>, <Sm>

Encoding for the Double-precision scalar variant

Applies when (size == 11)

VCMP{<c>}{<q>}.F64 <Dd>, <Dm>

Decode for all variants of this encoding

if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end; if size == '01' && cond != '1110' then UnpredictableProcedure(); end; let quiet_nan_exc : boolean = (E == '1'); let with_zero : boolean = FALSE; let esize : integer{} = 8 << UInt(size); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && cond != '1110', then one of the following behaviors must occur:

A2

313029282726252423222120191817161514131211109876543210
!= 111111101D110101Vd10size01(0)0(0)(0)(0)(0)
condo1opc2EMVm

Encoding for the Half-precision scalar variant
(FEAT_FP16)

Applies when (size == 01)

VCMP{<c>}{<q>}.F16 <Sd>, #0.0

Encoding for the Single-precision scalar variant

Applies when (size == 10)

VCMP{<c>}{<q>}.F32 <Sd>, #0.0

Encoding for the Double-precision scalar variant

Applies when (size == 11)

VCMP{<c>}{<q>}.F64 <Dd>, #0.0

Decode for all variants of this encoding

if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end; if size == '01' && cond != '1110' then UnpredictableProcedure(); end; let quiet_nan_exc : boolean = (E == '1'); let with_zero : boolean = TRUE; let esize : integer{} = 8 << UInt(size); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let m : integer = ARBITRARY : integer;

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && cond != '1110', then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111011101D110100Vd10size01M0Vm
o1opc2E

Encoding for the Half-precision scalar variant
(FEAT_FP16)

Applies when (size == 01)

VCMP{<c>}{<q>}.F16 <Sd>, <Sm>

Encoding for the Single-precision scalar variant

Applies when (size == 10)

VCMP{<c>}{<q>}.F32 <Sd>, <Sm>

Encoding for the Double-precision scalar variant

Applies when (size == 11)

VCMP{<c>}{<q>}.F64 <Dd>, <Dm>

Decode for all variants of this encoding

if size == '00' then Undefined(); end; if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end; if size == '01' && InITBlock() then UnpredictableProcedure(); end; let quiet_nan_exc : boolean = (E == '1'); let with_zero : boolean = FALSE; let esize : integer{} = 8 << UInt(size); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && InITBlock(), then one of the following behaviors must occur:

T2

15141312111098765432101514131211109876543210
111011101D110101Vd10size01(0)0(0)(0)(0)(0)
o1opc2EMVm

Encoding for the Half-precision scalar variant
(FEAT_FP16)

Applies when (size == 01)

VCMP{<c>}{<q>}.F16 <Sd>, #0.0

Encoding for the Single-precision scalar variant

Applies when (size == 10)

VCMP{<c>}{<q>}.F32 <Sd>, #0.0

Encoding for the Double-precision scalar variant

Applies when (size == 11)

VCMP{<c>}{<q>}.F64 <Dd>, #0.0

Decode for all variants of this encoding

if size == '00' then Undefined(); end; if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end; if size == '01' && InITBlock() then UnpredictableProcedure(); end; let quiet_nan_exc : boolean = (E == '1'); let with_zero : boolean = TRUE; let esize : integer{} = 8 << UInt(size); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let m : integer = ARBITRARY : integer;

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && InITBlock(), then one of the following behaviors must occur:

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>

Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); let fpcr : FPCR_Type = EffectiveFPCR(); var nzcv : bits(4); case esize of when 16 => let op16 : bits(16) = if with_zero then FPZero{16}('0') else H(m); nzcv = FPCompare{16}(H(d), op16, quiet_nan_exc, fpcr); when 32 => let op32 : bits(32) = if with_zero then FPZero{32}('0') else S(m); nzcv = FPCompare{32}(S(d), op32, quiet_nan_exc, fpcr); when 64 => let op64 : bits(64) = if with_zero then FPZero{64}('0') else D(m); nzcv = FPCompare{64}(D(d), op64, quiet_nan_exc, fpcr); end; FPSCR()[31:28] = nzcv; // FPSCR.[N,Z,C,V] set to nzcv end;

Operational information

The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either or both of the operands is a NaN, they are unordered, and all three of (Operand1 < Operand2), (Operand1 == Operand2) and (Operand1 > Operand2) are false. An unordered comparison sets the FPSCR condition flags to N=0, Z=0, C=1, and V=1.


2025-09_rel_asl1 2026-03-12 12:57:38

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