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VFMAL (vector)

Vector Floating-point Multiply-Add Long to accumulator (vector). This instruction multiplies corresponding values in the vectors in the two source SIMD&FP registers, and accumulates the product to the corresponding vector element of the destination SIMD&FP register. The instruction does not round the result of the multiply before the accumulation.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4 it is mandatory for all implementations to support it.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_FHM)

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FHM) then Undefined(); end; if Q == '1' && Vd[0] == '1' then Undefined(); end; let d : integer = UInt(D::Vd); let n : integer = if Q == '1' then UInt(N::Vn) else UInt(Vn::N); let m : integer = if Q == '1' then UInt(M::Vm) else UInt(Vm::M); let esize : integer{} = 32; let datasize : integer{} = 32 << UInt(Q); let sub_op : boolean = S == '1'; let regs : integer = if Q == '0' then 1 else 2;

T1
(FEAT_FHM)

Decode for all variants of this encoding

if InITBlock() then UnpredictableProcedure(); end; if !IsFeatureImplemented(FEAT_FHM) then Undefined(); end; if Q == '1' && Vd[0] == '1' then Undefined(); end; let d : integer = UInt(D::Vd); let n : integer = if Q == '1' then UInt(N::Vn) else UInt(Vn::N); let m : integer = if Q == '1' then UInt(M::Vm) else UInt(Vm::M); let esize : integer{} = 32; let regs : integer = 1 << UInt(Q); let datasize : integer{} = 32 << UInt(Q); let sub_op : boolean = S == '1';