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VMOVN -- AArch32

VMOVN

Vector Move and Narrow copies the least significant half of each element of a quadword vector into the corresponding elements of a doubleword vector.

The operand vector elements can be any one of 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

This instruction is used by the pseudo-instructions VRSHRN (zero), and VSHRN (zero).

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111100111D11size10Vd001000M0Vm
opc1opc2Q

Encoding

VMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>

Decode for this encoding

if size == '11' then Undefined(); end; if Vm[0] == '1' then Undefined(); end; let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

T1

15141312111098765432101514131211109876543210
111111111D11size10Vd001000M0Vm
opc1opc2Q

Encoding

VMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>

Decode for this encoding

if size == '11' then Undefined(); end; if Vm[0] == '1' then Undefined(); end; let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

Assembler Symbols

<c>

For the "A1" variant: see Standard assembler syntax fields. This encoding must be unconditional.

For the "T1" variant: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<dt>

Is the data type for the elements of the operand, encoded in size:

size <dt>
00 I16
01 I32
10 I64
11 RESERVED
<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Qm>

Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2025-09_rel_asl1 2026-03-12 12:57:38

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