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VMSR

Move general-purpose register to SIMD&FP Special register moves the value of a general-purpose register to a floating-point System register.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

When these settings permit the execution of Advanced SIMD and floating-point instructions:

• If the specified floating-point System register is FPSID or FPEXC, the instruction is UNDEFINED if executed in User mode.
• If the specified floating-point System register is the FPSID and the instruction is executed in a mode other than User mode, the instruction is ignored.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for this encoding

let t : integer = UInt(Rt); if reg != '000x' && reg != '1000' then let c : Constraint = ConstrainUnpredictable(Unpredictable_VMSR); assert c IN {Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNDEF => Undefined(); when Constraint_NOP => ExecuteAsNOP(); end; end; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If reg != '000x' && reg != '1000', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction transfers the value in the general-purpose register to one of the allocated registers accessible using VMSR at the same Exception level.

T1

Decode for this encoding

let t : integer = UInt(Rt); if reg != '000x' && reg != '1000' then let c : Constraint = ConstrainUnpredictable(Unpredictable_VMSR); assert c IN {Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNDEF => Undefined(); when Constraint_NOP => ExecuteAsNOP(); end; end; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If reg != '000x' && reg != '1000', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction transfers the value in the general-purpose register to one of the allocated registers accessible using VMSR at the same Exception level.

Assembler Symbols