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VPADDL

Vector Pairwise Add Long adds adjacent pairs of elements of two vectors, and places the results in the destination vector.

The vectors can be doubleword or quadword. The operand elements can be 8-bit, 16-bit, or 32-bit integers. The result elements are twice the length of the operand elements.

The following figure shows an example of the operation of VPADDL doubleword operation for data type S16.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for all variants of this encoding

if size == '11' then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let unsigned : boolean = (op == '1'); let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

T1

Decode for all variants of this encoding

if size == '11' then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let unsigned : boolean = (op == '1'); let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;