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VRSRA

Vector Rounding Shift Right and Accumulate takes each element in a vector, right shifts them by an immediate value, and accumulates the rounded results into the destination vector. For truncated results, see VSRA.

The operand and result elements must all be the same type, and can be any one of:

• 8-bit, 16-bit, 32-bit, or 64-bit signed integers.
• 8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for all variants of this encoding

if (L::imm6) == '0000xxx' then See("Related encodings"); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let esize : integer{} = 8 << HighestSetBitNZ((L::imm6)[6:3]); let elements : integer = 64 DIV esize; let shift_amount : integer = (esize * 2) - UInt(L::imm6); let unsigned : boolean = (U == '1'); let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

T1

Decode for all variants of this encoding

if (L::imm6) == '0000xxx' then See("Related encodings"); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let esize : integer{} = 8 << HighestSetBitNZ((L::imm6)[6:3]); let elements : integer = 64 DIV esize; let shift_amount : integer = (esize * 2) - UInt(L::imm6); let unsigned : boolean = (U == '1'); let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

Assembler Symbols