This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

VSHLL -- AArch32

VSHLL

Vector Shift Left Long takes each element in a doubleword vector, left shifts them by an immediate value, and places the results in a quadword vector.

The operand elements can be:

The result elements are twice the length of the operand elements.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
1111001U1D!= 000xxxVd101000M1Vm
imm6opcLQ

Encoding

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>

Decode for this encoding

if imm6 == '000xxx' then See("Related encodings"); end; if imm6 IN {'001000', '010000', '100000'} then See("VMOVL"); end; if Vd[0] == '1' then Undefined(); end; let esize : integer{} = 8 << HighestSetBitNZ(imm6[5:3]); let elements : integer = 64 DIV esize; let shift_amount : integer = UInt(imm6) - esize; let unsigned : boolean = (U == '1'); let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

A2

313029282726252423222120191817161514131211109876543210
111100111D11size10Vd001100M0Vm
opc1opc2Q

Encoding

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>

Decode for this encoding

if size == '11' || Vd[0] == '1' then Undefined(); end; let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let shift_amount : integer = esize; let unsigned : boolean = FALSE; // Or TRUE without change of functionality let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

T1

15141312111098765432101514131211109876543210
111U11111D!= 000xxxVd101000M1Vm
imm6opcLQ

Encoding

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>

Decode for this encoding

if imm6 == '000xxx' then See("Related encodings"); end; if imm6 IN {'001000', '010000', '100000'} then See("VMOVL"); end; if Vd[0] == '1' then Undefined(); end; let esize : integer{} = 8 << HighestSetBitNZ(imm6[5:3]); let elements : integer = 64 DIV esize; let shift_amount : integer = UInt(imm6) - esize; let unsigned : boolean = (U == '1'); let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

T2

15141312111098765432101514131211109876543210
111111111D11size10Vd001100M0Vm
opc1opc2Q

Encoding

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>

Decode for this encoding

if size == '11' || Vd[0] == '1' then Undefined(); end; let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let shift_amount : integer = esize; let unsigned : boolean = FALSE; // Or TRUE without change of functionality let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.

Assembler Symbols

<c>

For the "A1" and "A2" variants: see Standard assembler syntax fields. This encoding must be unconditional.

For the "T1" and "T2" variants: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<size>

The data size for the elements of the operand. The following table shows the permitted values and their encodings:

<size> Encoding T1/A1 Encoding T2/A2
8 Encoded as imm6<5:3> =0b001 Encoded as size =0b00
16 Encoded as imm6<5:4> =0b01 Encoded as size =0b01
32 Encoded as imm6<5> = 1 Encoded as size =0b10
<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dm>

Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>

The immediate value. <imm> must lie in the range 1 to <size>, and:

  • If <size> == <imm>, the encoding is T2/A2.
  • Otherwise, the encoding is T1/A1, and:

    • If <size> == 8, <imm> is encoded in imm6<2:0>.
    • If <size> == 16, <imm> is encoded in imm6<3:0>.
    • If <size> == 32, <imm> is encoded in imm6<4:0>.
<type>

The data type for the elements of the operand. It must be one of:

S
Signed. In encoding T1/A1, encoded as U = 0.
U
Unsigned. In encoding T1/A1, encoded as U = 1.
I
Untyped integer, Available only in encoding T2/A2.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for e = 0 to elements-1 do let opelt : bits(esize) = Din(m)[e*:esize]; let element : integer = if unsigned then UInt(opelt) else SInt(opelt); let result : integer = element << shift_amount; Q(d>>1)[e*:(2*esize)] = result[2*esize-1:0]; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2025-09_rel_asl1 2026-03-12 12:57:38

Copyright © 2010-2025 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.