VSLI -- AArch32

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VSLI -- AArch32

VSLI

Vector Shift Left and Insert takes each element in the operand vector, left shifts them by an immediate value, and inserts the results in the destination vector. Bits shifted out of the left of each element are lost.

The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit. There is no distinction between data types.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	0	1	1	1	D	imm6						Vd				0	1	0	1	L	Q	M	1	Vm
							U													opc

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0 && !(imm6[5:3] == 000 && L == 0))

VSLI{<c>}{<q>}.<size> {<Dd>, }<Dm>, #<imm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1 && !(imm6[5:3] == 000 && L == 0))

VSLI{<c>}{<q>}.<size> {<Qd>, }<Qm>, #<imm>

Decode for all variants of this encoding

if (L::imm6) == '0000xxx' then See("Related encodings"); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let esize : integer{} = 8 << HighestSetBitNZ((L::imm6)[6:3]); let elements : integer = 64 DIV esize; let shift_amount : integer = UInt(L::imm6) - esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	1	1	1	1	D	imm6						Vd				0	1	0	1	L	Q	M	1	Vm
			U																	opc

Assembler Symbols

<c>	For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
	For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<size>

Is the data size for the elements of the vectors, encoded in (L :: imm6):

L	imm6	<size>
0	001xxx	8
0	01xxxx	16
0	1xxxxx	32
1	xxxxxx	64

<Dd>	Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>	Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>

Is an immediate value, in the range 0 to <size>-1, encoded in the "imm6" field.

<Qd>	Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>	Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); let mask : bits(esize) = LSL{}(Ones{esize}, shift_amount); for r = 0 to regs-1 do for e = 0 to elements-1 do let shifted_op : bits(esize) = LSL{}(D(m+r)[e*:esize], shift_amount); D(d+r)[e*:esize] = (D(d+r)[e*:esize] AND NOT(mask)) OR shifted_op; end; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.

2025-09_rel_asl1 2026-03-12 12:57:38