VSTM, VSTMDB, VSTMIA -- AArch32

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VSTM, VSTMDB, VSTMIA

Store multiple SIMD&FP registers stores multiple registers from the Advanced SIMD and floating-point register file to consecutive memory locations using an address from a general-purpose register.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				1	1	0	P	U	D	W	0	Rn				Vd				1	0	1	1	x	x	x	x	x	x	x	0
cond											L											size		imm8

Encoding for the Increment After variant

Applies when (P == 0 && U == 1)

VSTM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist> // (Preferred syntax)

VSTMIA{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>

Decode for all variants of this encoding

if P == '0' && U == '0' && W == '0' then See("Related encodings"); end; if P == '1' && W == '0' then See("VSTR"); end; if P == U && W == '1' then Undefined(); end; // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) let single_regs : boolean = FALSE; let add : boolean = (U == '1'); let wback : boolean = (W == '1'); let d : integer = UInt(D::Vd); let n : integer = UInt(Rn); let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); let regs : integer = UInt(imm8) DIVRM 2; // If UInt(imm8) is odd, see "FSTDBMX, FSTMIAX". if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end; if regs == 0 || regs > 16 || (d+regs) > 32 then UnpredictableProcedure(); end; if imm8[0] == '1' && (d+regs) > 16 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

Encoding for the Increment After variant

Applies when (P == 0 && U == 1)

VSTM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist> // (Preferred syntax)

VSTMIA{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>

Decode for all variants of this encoding

if P == '0' && U == '0' && W == '0' then See("Related encodings"); end; if P == '1' && W == '0' then See("VSTR"); end; if P == U && W == '1' then Undefined(); end; // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) let single_regs : boolean = TRUE; let add : boolean = (U == '1'); let wback : boolean = (W == '1'); let d : integer = UInt(Vd::D); let n : integer = UInt(Rn); let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); let regs : integer = UInt(imm8); if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end; if regs == 0 || (d+regs) > 32 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

Encoding for the Increment After variant

Applies when (P == 0 && U == 1)

VSTM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist> // (Preferred syntax)

VSTMIA{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>

Decode for all variants of this encoding

CONSTRAINED UNPREDICTABLE behavior

Encoding for the Increment After variant

Applies when (P == 0 && U == 1)

VSTM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist> // (Preferred syntax)

VSTMIA{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>

Decode for all variants of this encoding

if P == '0' && U == '0' && W == '0' then See("Related encodings"); end; if P == '1' && W == '0' then See("VSTR"); end; if P == U && W == '1' then Undefined(); end; // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) let single_regs : boolean = TRUE; let add : boolean = (U == '1'); let wback : boolean = (W == '1'); let d : integer = UInt(Vd::D); let n : integer = UInt(Rn); let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); let regs : integer = UInt(imm8); if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end; if regs == 0 || (d+regs) > 32 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VSTM.

Related encodings: See Advanced SIMD and floating-point 64-bit move for the T32 instruction set, or Advanced SIMD and floating-point 64-bit move for the A32 instruction set.

Assembler Symbols

Alias Conditions

Alias	Is preferred when
VPUSH	P == '1' && U == '0' && W == '1' && Rn == '1101'

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); var address : bits(32) = if add then R(n) else R(n)-imm32; for r = 0 to regs-1 do if single_regs then MemA{32}(address) = S(d+r); address = address+4; else // Store as two word-aligned words in the correct order for current endianness. if BigEndian(AccessType_ASIMD) then MemA{32}(address) = D(d+r)[63:32]; MemA{32}(address+4) = D(d+r)[31:0]; else MemA{32}(address) = D(d+r)[31:0]; MemA{32}(address+4) = D(d+r)[63:32]; end; address = address+8; end; end; if wback then R(n) = if add then R(n)+imm32 else R(n)-imm32; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.

2025-09_rel_asl1 2026-03-12 12:57:38