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VSTR -- AArch32

VSTR

Store SIMD&FP register stores a single register from the Advanced SIMD and floating-point register file to memory, using an address from a general-purpose register, with an optional offset.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 11111101UD00RnVd10sizeimm8
condPWL

Encoding for the Half-precision scalar variant
(FEAT_FP16)

Applies when (size == 01)

VSTR{<c>}{<q>}.16 <Sd>, [<Rn>{, #{+/-}<imm>}]

Encoding for the Single-precision scalar variant

Applies when (size == 10)

VSTR{<c>}{<q>}{.32} <Sd>, [<Rn>{, #{+/-}<imm>}]

Encoding for the Double-precision scalar variant

Applies when (size == 11)

VSTR{<c>}{<q>}{.64} <Dd>, [<Rn>{, #{+/-}<imm>}]

Decode for all variants of this encoding

if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end; if size == '01' && cond != '1110' then UnpredictableProcedure(); end; let add : boolean = (U == '1'); let esize : integer{} = 8 << UInt(size); let imm32 : integer = UInt(imm8) << (if size == '01' then 1 else 2); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let n : integer = UInt(Rn); if n == 15 && CurrentInstrSet() != InstrSet_A32 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && cond != '1110', then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
11101101UD00RnVd10sizeimm8
PWL

Encoding for the Half-precision scalar variant
(FEAT_FP16)

Applies when (size == 01)

VSTR{<c>}{<q>}.16 <Sd>, [<Rn>{, #{+/-}<imm>}]

Encoding for the Single-precision scalar variant

Applies when (size == 10)

VSTR{<c>}{<q>}{.32} <Sd>, [<Rn>{, #{+/-}<imm>}]

Encoding for the Double-precision scalar variant

Applies when (size == 11)

VSTR{<c>}{<q>}{.64} <Dd>, [<Rn>{, #{+/-}<imm>}]

Decode for all variants of this encoding

if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end; if size == '01' && InITBlock() then UnpredictableProcedure(); end; let add : boolean = (U == '1'); let esize : integer{} = 8 << UInt(size); let imm32 : integer = UInt(imm8) << (if size == '01' then 1 else 2); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let n : integer = UInt(Rn); if n == 15 && CurrentInstrSet() != InstrSet_A32 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && InITBlock(), then one of the following behaviors must occur:

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Sd>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Vd:D" field.

<Rn>

Is the general-purpose base register, encoded in the "Rn" field. The PC can be used, but this is deprecated.

+/-

Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:

U +/-
0 -
1 +
<imm>

For the "A1 Half-precision scalar" and "T1 Half-precision scalar" variants: is the optional unsigned immediate byte offset, a multiple of 2, in the range 0 to 510, defaulting to 0, and encoded in the "imm8" field as <imm>/2.

For the "A1 Double-precision scalar", "A1 Single-precision scalar", "T1 Double-precision scalar", and "T1 Single-precision scalar" variants: is the optional unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0, and encoded in the "imm8" field as <imm>/4.

.32

Is an optional data size specifier for 32-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.

.64

Is an optional data size specifier for 64-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.

<Dd>

Is the 64-bit name of the SIMD&FP source register, encoded in the "D:Vd" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); let address : bits(32) = if add then (R(n) + imm32) else (R(n) - imm32); case esize of when 16 => MemA{16}(address) = H(d); when 32 => MemA{32}(address) = S(d); when 64 => // Store as two word-aligned words in the correct order for current endianness. if BigEndian(AccessType_ASIMD) then MemA{32}(address) = D(d)[63:32]; MemA{32}(address+4) = D(d)[31:0]; else MemA{32}(address) = D(d)[31:0]; MemA{32}(address+4) = D(d)[63:32]; end; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2025-09_rel_asl1 2026-03-12 12:57:38

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