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VUZP -- AArch32

VUZP

Vector Unzip de-interleaves the elements of two vectors.

The elements of the vectors can be 8-bit, 16-bit, or 32-bit. There is no distinction between data types.

The following figure shows an example of the operation of VUZP doubleword operation for data type 8.
VUZP doubleword operation for data type 8

The following figure shows an example of the operation of VUZP quadword operation for data type 32.
VUZP quadword operation for data type 32

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111100111D11size10Vd00010QM0Vm
opc1opc2

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VUZP{<c>}{<q>}.<dt> <Dd>, <Dm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VUZP{<c>}{<q>}.<dt> <Qd>, <Qm>

Decode for all variants of this encoding

if size == '11' || (Q == '0' && size == '10') then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let quadword_operation : boolean = (Q == '1'); let esize : integer{} = 8 << UInt(size); let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

T1

15141312111098765432101514131211109876543210
111111111D11size10Vd00010QM0Vm
opc1opc2

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VUZP{<c>}{<q>}.<dt> <Dd>, <Dm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VUZP{<c>}{<q>}.<dt> <Qd>, <Qm>

Decode for all variants of this encoding

if size == '11' || (Q == '0' && size == '10') then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let quadword_operation : boolean = (Q == '1'); let esize : integer{} = 8 << UInt(size); let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

Assembler Symbols

<c>

For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.

For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<dt>

For the "A1 64-bit SIMD vector" and "T1 64-bit SIMD vector" variants: is the data type for the elements of the vectors, encoded in size:

size <dt>
00 8
01 16
1x RESERVED

For the "A1 128-bit SIMD vector" and "T1 128-bit SIMD vector" variants: is the data type for the elements of the vectors, encoded in size:

size <dt>
00 8
01 16
10 32
11 RESERVED
<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>

Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>

Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2025-09_rel_asl1 2026-03-12 12:57:38

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