ADD (immediate, to PC) Add to PC Add to PC adds an immediate value to the Align(PC, 4) value to form a PC-relative address, and writes the result to the destination register. Arm recommends that, where possible, software avoids using this alias. ADR It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T3 ) . != 1111 0 0 1 0 1 0 0 0 1 1 1 1 ADD{<c>}{<q>} <Rd>, PC, #<const> ADR{<c>}{<q>} <Rd>, <label> Never 1 0 1 0 0 ADD{<c>}{<q>} <Rd>, PC, #<imm8> ADR{<c>}{<q>} <Rd>, <label> Never 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 ADD{<c>}{<q>} <Rd>, PC, #<imm12> ADDW{<c>}{<q>} <Rd>, PC, #<imm12> ADR{<c>}{<q>} <Rd>, <label> Never <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> For the "T1" and "T3" variants: is the general-purpose destination register, encoded in the "Rd" field. <Rd> For the "A1" variant: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. <imm12> Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field. <const> An immediate value. See Modified immediate constants in A32 instructions for the range of values. <imm8> Is an unsigned immediate, a multiple of 4, in the range 0 to 1020, encoded in the "imm8" field as <imm8>/4. 2026-03-26 20:27:25 2026-03_rel