BX Branch and Exchange Branch and Exchange causes a branch to an address and instruction set specified by a register. For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 0 1 BX{<c>}{<q>} <Rm> let m : integer = UInt(Rm); 0 1 0 0 0 1 1 1 0 (0) (0) (0) BX{<c>}{<q>} <Rm> let m : integer = UInt(Rm); if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rm> For the "A1" variant: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used. <Rm> For the "T1" variant: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used. If <Rm> is the PC at a non word-aligned address, it results in UNPREDICTABLE behavior because the address passed to the BXWritePC() pseudocode function has bits<1:0> = '10'. if ConditionPassed() then EncodingSpecificOperations(); BXWritePC(R(m), BranchType_INDIR); end; 2026-03-26 20:27:25 2026-03_rel