BXJ Branch and Exchange, previously Branch and Exchange Jazelle Branch and Exchange, previously Branch and Exchange Jazelle. BXJ behaves as a BX instruction, see BX. This means it causes a branch to an address and instruction set specified by a register. For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 0 BXJ{<c>}{<q>} <Rm> let m : integer = UInt(Rm); if m == 15 then UnpredictableProcedure(); end; 1 1 1 1 0 0 1 1 1 1 0 0 1 0 (0) 0 (1) (1) (1) (1) (0) (0) (0) (0) (0) (0) (0) (0) BXJ{<c>}{<q>} <Rm> let m : integer = UInt(Rm); // Armv8-A removes UNPREDICTABLE for R13 if m == 15 then UnpredictableProcedure(); end; if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rm> Is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. if ConditionPassed() then EncodingSpecificOperations(); BXWritePC(R(m), BranchType_INDIR); end; 2026-03-26 20:27:25 2026-03_rel