CMN (register)
Compare Negative (register)
Compare Negative (register) adds a register value and an
optionally-shifted register value. It updates the condition flags
based on the result, and discards the result.
For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
0
0
1
0
1
1
1
(0)
(0)
(0)
(0)
0
0
0
0
0
0
1
1
CMN{<c>}{<q>} <Rn>, <Rm>, RRX
CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount>}
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm5);
0
1
0
0
0
0
1
0
1
1
CMN{<c>}{<q>} <Rn>, <Rm>
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let shift_t : SRType = SRType_LSL;
let shift_n : integer = 0;
1
1
1
0
1
0
1
1
0
0
0
1
(0)
1
1
1
1
0
0
0
0
0
1
1
CMN{<c>}{<q>} <Rn>, <Rm>, RRX
CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount>}
CMN{<c>}.W <Rn>, <Rm>
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm3::imm2);
// Armv8-A removes UNPREDICTABLE for R13
if n == 15 || m == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rn>
For the "A1 Rotate right with extend" and "A1 Shift or rotate by value" variants: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.
<Rn>
For the "T1", "T2 Rotate right with extend", and "T2 Shift or rotate by value" variants: is the first general-purpose source register, encoded in the "Rn" field.
<Rm>
For the "A1 Rotate right with extend" and "A1 Shift or rotate by value" variants: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.
<Rm>
For the "T1", "T2 Rotate right with extend", and "T2 Shift or rotate by value" variants: is the second general-purpose source register, encoded in the "Rm" field.
<shift>
Is the type of shift to be applied to the second source register,
stype
<shift>
00
LSL
01
LSR
10
ASR
11
ROR
<amount>
For the "A1 Shift or rotate by value" variant: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.
<amount>
For the "T2 Shift or rotate by value" variant: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32.
if ConditionPassed() then
EncodingSpecificOperations();
let shifted : bits(32) = Shift{}(R(m), shift_t, shift_n, PSTATE.C);
let (result, nzcv) : (bits(32), bits(4)) = AddWithCarry{32}(R(n), shifted, '0');
PSTATE.[N,Z,C,V] = nzcv;
end;
2026-03-26 20:27:25
2026-03_rel