<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="LDA" title="LDA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="mnemonic" value="LDA"/>
  </docvars>
  <heading>LDA</heading>
  <desc>
    <brief>
      <para>Load-Acquire Word</para>
    </brief>
    <authored>
      <para>Load-Acquire Word loads a word from memory and writes it to
a register. The instruction also has memory ordering semantics as
described in <xref linkend="ARMARM_AA32CHDBDIDF">Load-Acquire, Store-Release</xref></para>
      <para>For more information about support for shared memory see
<xref linkend="ARMARM_CEGDAEAG">Synchronization and semaphores</xref>. For
information about memory accesses see <xref linkend="ARMARM_Chddjfjf">Memory
accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> behavior, see <xref linkend="ARMARM_CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEIIDCEG">About the DIT bit</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A32"/>
        <docvar key="mnemonic" value="LDA"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A32.dp.sync.ldst_excl.LDA_A1" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="8" name="ord" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="7" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" usename="1" settings="4" psbits="xxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDA_A1" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="LDA"/>
        </docvars>
        <asmtemplate><text>LDA{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="c__5">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field." link="Rt">&lt;Rt&gt;</a><text>, [</text><a hover="Is the general-purpose base register, encoded in the &quot;Rn&quot; field." link="Rn__12">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A32.dp.sync.ldst_excl.LDA_A1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
if t == 15 || n == 15 then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="LDA"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="16x2" psname="T32.w.dstd.ldastl.LDA_T1" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op0" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="4" name="Rt2" usename="1" settings="4" psbits="xxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="sz" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" usename="1" settings="4" psbits="xxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDA_T1" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="LDA"/>
        </docvars>
        <asmtemplate><text>LDA{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="c__5">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field." link="Rt">&lt;Rt&gt;</a><text>, [</text><a hover="Is the general-purpose base register, encoded in the &quot;Rn&quot; field." link="Rn__12">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.dstd.ldastl.LDA_T1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
if t == 15 || n == 15 then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDA_A1, LDA_T1" symboldefcount="1">
      <symbol link="c__5">&lt;c&gt;</symbol>
      <account encodedin="cond">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDA_A1, LDA_T1" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDA_A1, LDA_T1" symboldefcount="1">
      <symbol link="Rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDA_A1, LDA_T1" symboldefcount="1">
      <symbol link="Rn__12">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A32.dp.sync.ldst_excl.LDA_A1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="func_ConditionPassed_0" file="shared_pseudocode.xml">ConditionPassed</a>() then
    EncodingSpecificOperations();
    let address : bits(32) = <a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(n);
    <a link="accessor_R_1" file="shared_pseudocode.xml">R</a>(t) = <a link="accessor_MemO_2" file="shared_pseudocode.xml">MemO</a>{32}(address);
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>