LDC (literal)
Load data to System register (literal)
Load data to System register (literal) calculates an address from
the PC value and an immediate offset, loads a word from memory, and
writes it to the DBGDTRTXint
System register. For information about memory accesses, see
Memory accesses.
In an implementation that includes EL2, the permitted LDC
access to DBGDTRTXint can be
trapped to Hyp mode, meaning that an attempt to execute an LDC
instruction in a Non-secure mode other than Hyp mode, that would be
permitted in the absence of the Hyp trap controls, generates a Hyp
Trap exception. For more information, see
HDCR.TDA.
For simplicity, the LDC pseudocode does not show this possible
trap to Hyp mode.
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
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LDC{<c>}{<q>} p14, c5, <label>
LDC{<c>}{<q>} p14, c5, [PC, #{+/-}<imm>]
LDC{<c>}{<q>} p14, c5, [PC], <option>
if P == '0' && U == '0' && W == '0' then Undefined(); end;
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let cp : integer = 14;
let imm32 : bits(32) = ZeroExtend{}(imm8::'00');
if W == '1' || (P == '0' && CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end;
W == '1'
The instruction uses the addressing mode described in the equivalent immediate offset instruction.
1
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LDC{<c>}{<q>} p14, c5, <label>
LDC{<c>}{<q>} p14, c5, [PC, #{+/-}<imm>]
if P == '0' && U == '0' && W == '0' then Undefined(); end;
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let cp : integer = 14;
let imm32 : bits(32) = ZeroExtend{}(imm8::'00');
if W == '1' || (P == '0' && CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end;
W == '1' || P == '0'
The instruction executes as LDC (immediate) with writeback to the PC. The instruction is handled as described in Using R15.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<label>
The label of the literal data item that is to be loaded into <Rt>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Permitted values of the offset are multiples of 4 in the range -1020 to 1020.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE (encoded as U == 1).
If the offset is negative, imm32 is equal to minus the offset and add == FALSE (encoded as U == 0).
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting to 0 and encoded in the "imm8" field, as <imm>/4.
<option>
Is an 8-bit immediate, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field. The value of this field is ignored when executing this instruction.
if ConditionPassed() then
EncodingSpecificOperations();
let offset_addr : bits(32) = (if add then (AlignDownSize(PC32(),4) + imm32)
else (AlignDownSize(PC32(),4) - imm32));
let address : bits(32) = if index then offset_addr else AlignDownSize(PC32(),4);
// System register write to DBGDTRTXint.
AArch32_SysRegWriteM(cp, ThisInstr(), address);
end;
2026-03-26 20:27:25
2026-03_rel