LDM, LDMIA, LDMFD Load Multiple (Increment After, Full Descending) Load Multiple (Increment After, Full Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the highest of those locations can optionally be written back to the base register. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also Encoding of lists of general-purpose registers and the PC. Armv8.2 permits the deprecation of some Load Multiple ordering behaviors in AArch32 state, for more information see FEAT_LSMAOC. The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. Related system instructions are LDM (User registers) and LDM (exception return). For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. This instruction is a data-independent-time instruction as described in About the DIT bit. This instruction is used by the alias POP (multiple registers) W == '1' && Rn == '1101' && BitCount(register_list) > 1 W == '1' && Rn == '1101' && BitCount(P :: M :: register_list) > 1 BitCount(P :: M :: register_list) > 1 See below for details of when the alias is preferred. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) . != 1111 1 0 0 0 1 0 1 LDM{IA}{<c>}{<q>} <Rn>{!}, <registers> LDMFD{<c>}{<q>} <Rn>{!}, <registers> let n : integer = UInt(Rn); let registers : bits(16) = register_list; let wback : boolean = (W == '1'); if n == 15 || BitCount(registers) < 1 then UnpredictableProcedure(); end; if wback && registers[n] == '1' then UnpredictableProcedure(); end; BitCount(registers) < 1 The instruction executes as LDM with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded. wback && registers<n> == '1' The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated. 1 1 0 0 1 LDM{IA}{<c>}{<q>} <Rn>{!}, <registers> LDMFD{<c>}{<q>} <Rn>{!}, <registers> let n : integer = UInt(Rn); let registers : bits(16) = '00000000'::register_list; let wback : boolean = (registers[n] == '0'); if BitCount(registers) < 1 then UnpredictableProcedure(); end; BitCount(registers) < 1 The instruction executes as LDM with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded. 1 1 1 0 1 0 0 0 1 0 1 LDM{IA}{<c>}.W <Rn>{!}, <registers> LDMFD{<c>}.W <Rn>{!}, <registers> LDM{IA}{<c>}{<q>} <Rn>{!}, <registers> LDMFD{<c>}{<q>} <Rn>{!}, <registers> let n : integer = UInt(Rn); let registers : bits(16) = P::M::register_list; let wback : boolean = (W == '1'); if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UnpredictableProcedure(); end; if wback && registers[n] == '1' then UnpredictableProcedure(); end; if registers[13] == '1' then UnpredictableProcedure(); end; if registers[15] == '1' && InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end; BitCount(registers) < 1 The instruction executes as LDM with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded. wback && registers<n> == '1' The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated. BitCount(registers) == 1 The instruction loads a single register using the specified addressing modes. The instruction executes as LDM with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. registers<13> == '1' The instruction performs all of the loads using the specified addressing mode, but R13 is UNKNOWN. P == '1' && M == '1' The instruction loads the register list and either R14 or R15, both R14 and R15, or neither of these registers. IA Is an optional suffix for the Increment After form. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rn> Is the general-purpose base register, encoded in the "Rn" field. ! For the "A1" and "T2" variants: the address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0. ! For the "T1" variant: the address adjusted by the size of the data loaded is written back to the base register. It is omitted if <Rn> is included in <registers>, otherwise it must be present. <registers> For the "A1" variant: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The PC can be in the list. Arm deprecates using these instructions with both the LR and the PC in the list. <registers> For the "T1" variant: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The registers in the list must be in the range R0-R7, encoded in the "register_list" field. <registers> For the "T2" variant: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain one of the LR or the PC. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0. If the PC is in the list, the "P" field is set to 1, otherwise it defaults to 0. If the PC is in the list: The LR must not be in the list. The instruction must be either outside any IT block, or the last instruction in an IT block. Alias Conditions if ConditionPassed() then EncodingSpecificOperations(); var address : bits(32) = R(n); var data : bits(32); for i = 0 to 14 do if registers[i] == '1' then if i != n then R(i) = MemS{32}(address); else data = MemS{32}(address); end; address = address + 4; end; end; if registers[15] == '1' then LoadWritePC(MemS{32}(address)); end; if wback && registers[n] == '1' then R(n) = ARBITRARY : bits(32); end; if wback && registers[n] == '0' then R(n) = R(n) + 4*BitCount(registers); end; if !wback && registers[n] == '1' then R(n) = data; end; end; 2026-03-26 20:27:25 2026-03_rel