LDRD (literal)
Load Register Dual (literal)
Load Register Dual (literal) calculates an address from the PC value
and an immediate offset, loads two words from memory, and writes
them to two registers. For information about memory accesses see
Memory accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related encodings: Load/Store dual, Load/Store-Exclusive, Load-Acquire/Store-Release, table branch.
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
0
0
0
(1)
1
(0)
0
1
1
1
1
1
1
0
1
LDRD{<c>}{<q>} <Rt>, <Rt2>, <label>
LDRD{<c>}{<q>} <Rt>, <Rt2>, [PC, #{+/-}<imm>]
if Rt[0] == '1' then UnpredictableProcedure(); end;
let t : integer = UInt(Rt);
let t2 : integer = t + 1;
let imm32 : bits(32) = ZeroExtend{}(imm4H::imm4L);
let add : boolean = (U == '1');
if t2 == 15 then UnpredictableProcedure(); end;
Rt<0> == '1'
The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.
P == '0' || W == '1'
The instruction executes as if P == 1 and W == 0.'
1
1
1
0
1
0
0
1
1
1
1
1
1
LDRD{<c>}{<q>} <Rt>, <Rt2>, <label>
LDRD{<c>}{<q>} <Rt>, <Rt2>, [PC, #{+/-}<imm>]
if P == '0' && W == '0' then See("Related encodings"); end;
let t : integer = UInt(Rt);
let t2 : integer = UInt(Rt2);
let imm32 : bits(32) = ZeroExtend{}(imm8::'00');
let add : boolean = (U == '1');
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 || t2 == 15 || t == t2 then UnpredictableProcedure(); end;
if W == '1' then UnpredictableProcedure(); end;
t == t2
W == '1'
The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in Using R15.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
For the "A1" variant: is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.
<Rt>
For the "T1" variant: is the first general-purpose register to be transferred, encoded in the "Rt" field.
<Rt2>
For the "A1" variant: is the second general-purpose register to be transferred. This register must be <R(t+1)>.
<Rt2>
For the "T1" variant: is the second general-purpose register to be transferred, encoded in the "Rt2" field.
<label>
For the "A1" variant: the label of the literal data item that is to be loaded into <Rt>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Any value in the range -255 to 255 is permitted.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE, encoded as U == 1. If the offset is negative, imm32 is equal to minus the offset and add == FALSE, encoded as U == 0.
<label>
For the "T1" variant: the label of the literal data item that is to be loaded into <Rt>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Permitted values of the offset are multiples of 4 in the range -1020 to 1020.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE, encoded as U == 1.
If the offset is negative, imm32 is equal to minus the offset and add == FALSE, encoded as U == 0.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For the "A1" variant: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.
<imm>
For the "T1" variant: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.
if ConditionPassed() then
EncodingSpecificOperations();
let address : bits(32) = (if add then (AlignDownSize(PC32(),4) + imm32)
else (AlignDownSize(PC32(),4) - imm32));
if IsAlignedSize(address, 8) then
let data : bits(64) = MemA{64}(address);
if BigEndian(AccessType_GPR) then
R(t) = data[63:32];
R(t2) = data[31:0];
else
R(t) = data[31:0];
R(t2) = data[63:32];
end;
else
let data1 : bits(32) = MemA{32}(address);
let data2 : bits(32) = MemA{32}(address+4);
R(t) = data1;
R(t2) = data2;
end;
end;
2026-03-26 20:27:25
2026-03_rel