LDRSH (literal)
Load Register Signed Halfword (literal)
Load Register Signed Halfword (literal) calculates an address
from the PC value and an immediate offset, loads a halfword from
memory, sign-extends it to form a 32-bit word, and writes it to
a register. For information about memory accesses see Memory accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related instructions: Load, signed (literal).
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
0
0
0
1
1
1
1
1
1
1
1
1
1
LDRSH{<c>}{<q>} <Rt>, <label>
LDRSH{<c>}{<q>} <Rt>, [PC, #{+/-}<imm>]
if P == '0' && W == '1' then See("LDRSHT"); end;
let t : integer = UInt(Rt);
let imm32 : bits(32) = ZeroExtend{}(imm4H::imm4L);
let add : boolean = (U == '1');
let wback : boolean = (P == '0') || (W == '1');
if t == 15 || wback then UnpredictableProcedure(); end;
wback
The instruction treats bit[24] as the P bit, and bit[21] as the writeback (W) bit, and uses the same addressing mode as described in LDRSH (immediate). The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in Using R15.
1
1
1
1
1
0
0
1
0
1
1
1
1
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1
!= 1111
LDRSH{<c>}{<q>} <Rt>, <label>
LDRSH{<c>}{<q>} <Rt>, [PC, #{+/-}<imm>]
if Rt == '1111' then See("Related instructions"); end;
let t : integer = UInt(Rt);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let add : boolean = (U == '1');
// Armv8-A removes UNPREDICTABLE for R13
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
Is the general-purpose register to be transferred, encoded in the "Rt" field.
<label>
For the "A1" variant: the label of the literal data item that is to be loaded into <Rt>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Any value in the range -255 to 255 is permitted.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE, encoded as U == 1. If the offset is negative, imm32 is equal to minus the offset and add == FALSE, encoded as U == 0.
<label>
For the "T1" variant: the label of the literal data item that is to be loaded into <Rt>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Permitted values of the offset are -4095 to 4095.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE, encoded as U == 1.
If the offset is negative, imm32 is equal to minus the offset and add == FALSE, encoded as U == 0.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For the "A1" variant: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.
<imm>
For the "T1" variant: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.
if ConditionPassed() then
EncodingSpecificOperations();
let base : bits(32) = AlignDownSize(PC32(),4);
let address : bits(32) = if add then (base + imm32) else (base - imm32);
let data : bits(16) = MemU{16}(address);
R(t) = SignExtend{32}(data);
end;
2026-03-26 20:27:25
2026-03_rel