LDRSH (register)
Load Register Signed Halfword (register)
Load Register Signed Halfword (register) calculates an address
from a base register value and an offset register value, loads a
halfword from memory, sign-extends it to form a 32-bit word, and
writes it to a register. The offset register value can be shifted
left by 0, 1, 2, or 3 bits. For information about memory accesses
see Memory accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related instructions: Load/store, signed (register offset).
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
0
0
0
1
(0)
(0)
(0)
(0)
1
1
1
1
1
0
LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>]
0
0
LDRSH{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>
1
1
LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>]!
if P == '0' && W == '1' then See("LDRSHT"); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (P == '0') || (W == '1');
let shift_t : SRType = SRType_LSL;
let shift_n : integer = 0;
if t == 15 || m == 15 then UnpredictableProcedure(); end;
if wback && (n == 15 || n == t) then UnpredictableProcedure(); end;
wback && n == t
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.
0
1
0
1
1
1
1
LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>]
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
let shift_t : SRType = SRType_LSL;
let shift_n : integer = 0;
1
1
1
1
1
0
0
1
0
0
1
1
!= 1111
!= 1111
0
0
0
0
0
0
LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}]
LDRSH{<c>}.W <Rt>, [<Rn>, {+}<Rm>]
if Rn == '1111' then See("LDRSH (literal)"); end;
if Rt == '1111' then See("Related instructions"); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
let shift_t : SRType = SRType_LSL;
let shift_n : integer = UInt(imm2);
// Armv8-A removes UNPREDICTABLE for R13
if m == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>
For the "A1 Offset", "A1 Post-indexed", and "A1 Pre-indexed" variants: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.
<Rn>
For the "T1" and "T2" variants: is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
<Rm>
Is the general-purpose index register, encoded in the "Rm" field.
+
Specifies the index register is added to the base register.
<imm>
If present, the size of the left shift to apply to the value from <Rm>, in the range 1-3. <imm> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as 0b00.
if ConditionPassed() then
EncodingSpecificOperations();
let offset : bits(32) = Shift{}(R(m), shift_t, shift_n, PSTATE.C);
let offset_addr : bits(32) = if add then (R(n) + offset) else (R(n) - offset);
let address : bits(32) = if index then offset_addr else R(n);
let data : bits(16) = MemU{16}(address);
if wback then R(n) = offset_addr; end;
R(t) = SignExtend{32}(data);
end;
2026-03-26 20:27:25
2026-03_rel